• JEDEC JEP 122E

JEDEC JEP 122E

  • FAILURE MECHANISMS AND MODELS FOR SEMICONDUCTOR DEVICES
  • standard by JEDEC Solid State Technology Association, 03/01/2009
  • Category: JEDEC

$141.00 $71.00

This publication provides a list of failure mechanisms and their associated activation energies or acceleration factors that may be used in making system failure rate estimations when the only available data is based on tests performed at accelerated stress test conditions. The method to be used is the Sum of the Failure Rates method.
PDF

All of our standards document are available in PDF (Portable Document Format), an electronic, downloadable format.You will be able to download the file in your account downloads.

Multi-User Access

After purchasing, you have the ability to assign each license to a specific user.

Printable

At any time, you are permitted to make printed copies for your and your members' reference use.

JEDEC JESD55

JEDEC JESD55

STANDARD FOR DESCRIPTION OF LOW-VOLTAGE TTL-COMPATIBLE BiCMOS LOGIC DEVICES..

$31.00 $62.00

JEDEC JESD 36

JEDEC JESD 36

STANDARD DESCRIPTION OF LOW-VOLTAGE TTL-COMPATIBLE, 5 V TOLERANT CMOS LOGIC DEVICES..

$28.00 $56.00

JEDEC JESD32

JEDEC JESD32

STANDARD FOR CHAIN DESCRIPTION FILE..

$30.00 $59.00

JEDEC JEP103A (R2003)

JEDEC JEP103A (R2003)

SUGGESTED PRODUCT-DOCUMENTATION, CLASSIFICATIONS, AND DISCLAIMERS..

$24.00 $48.00