• JEDEC JEP156A

JEDEC JEP156A

  • CHIP-PACKAGE INTERACTION UNDERSTANDING, IDENTIFICATION AND EVALUATION
  • standard by JEDEC Solid State Technology Association, 03/01/2018
  • Category: JEDEC

$67.00 $34.00

This publication references a set of frequently recommended and accepted JEDEC reliability stress tests. These tests are used for qualifying new and modified technology/ process/ product families, as well as individual solid state surface-mount products.
PDF

All of our standards document are available in PDF (Portable Document Format), an electronic, downloadable format.You will be able to download the file in your account downloads.

Multi-User Access

After purchasing, you have the ability to assign each license to a specific user.

Printable

At any time, you are permitted to make printed copies for your and your members' reference use.

JEDEC JESD90

JEDEC JESD90

A PROCEDURE FOR MEASURING P-CHANNEL MOSFET NEGATIVE BIAS TEMPERATURE INSTABILITIES..

$30.00 $60.00

JEDEC JESD8-16A

JEDEC JESD8-16A

BUS INTERCONNECT LOGIC (BIC) FOR 1.2 V..

$34.00 $67.00

JEDEC JESD8-17

JEDEC JESD8-17

DRIVER SPECIFICATIONS FOR 1.8 V POWER SUPPLY POINT-TO-POINT DRIVERS..

$26.00 $51.00

JEDEC JEP149

JEDEC JEP149

APPLICATION THERMAL DERATING METHODOLOGIES..

$30.00 $59.00