• JEDEC JEP156A

JEDEC JEP156A

  • CHIP-PACKAGE INTERACTION UNDERSTANDING, IDENTIFICATION AND EVALUATION
  • standard by JEDEC Solid State Technology Association, 03/01/2018
  • Category: JEDEC

$67.00 $34.00

This publication references a set of frequently recommended and accepted JEDEC reliability stress tests. These tests are used for qualifying new and modified technology/ process/ product families, as well as individual solid state surface-mount products.
PDF

All of our standards document are available in PDF (Portable Document Format), an electronic, downloadable format.You will be able to download the file in your account downloads.

Multi-User Access

After purchasing, you have the ability to assign each license to a specific user.

Printable

At any time, you are permitted to make printed copies for your and your members' reference use.

JEDEC JESD47J

JEDEC JESD47J

STRESS-TEST-DRIVEN QUALIFICATION OF INTEGRATED CIRCUITS..

$37.00 $74.00

JEDEC JESD8-30

JEDEC JESD8-30

POD125 - 1.25 V PSEUDO OPEN DRAIN I/O..

$30.00 $60.00

JEDEC JESD47J.01

JEDEC JESD47J.01

STRESS-TEST-DRIVEN QUALIFICATION OF INTEGRATED CIRCUITS..

$37.00 $74.00

JEDEC JESD245B.01

JEDEC JESD245B.01

Byte Addressable Energy Backed Interface..

$96.00 $191.00