JEDEC JEP171
- GDDR5 Measurement Procedures
- standard by JEDEC Solid State Technology Association, 2014
- Category: JEDEC
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This publication is to inform all industry participants of a unified procedure to enable consistent measurement across the industry. This document contains the measurement procedures for testing GDDR5.
This document provides the test methodology details on:
This document provides the test methodology details on:
- CK and WCK Timings: tCK, tWCK, tCH/tCL, tWCKH/tWCKL, CK TJ/RJrms, CK and WCK Jitter
- CK and WCK Input Operating Conditions: VIXCK, VIXWCK, VIDCK(ac), VIDWCK(ac), VIDCK(dc),VIDWCK(dc), CKslew, and WCKslew
- Data Input Timings: tDIVW, tDIPW
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