• JEDEC JESD12

JEDEC JESD12

  • SEMICUSTOM INTEGRATED CIRCUITS (FORMERLY PUBLISHED AS STANDARD FOR GATE ARRAY BENCHMARK SET)
  • standard by JEDEC Solid State Technology Association, 06/01/1985
  • Category: JEDEC

$54.00 $27.00

The purpose of these benchmarks is to provide a common set of high level functions which serve as vehicles for comparing the performance of gate arrays implemented in any technology using any internal structure. These benchmarks effectively provide an unbiased measure of gate array vendors' ability to implement a desired complex function on a particular gate array at a known level of performance.
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JEDEC JESD213

JEDEC JESD213

STANDARD TEST METHOD UTILIZING X-RAY FLUORESCENCE (XRF) FOR ANALYZING COMPONENT FINISHES AND SOLDER ..

$27.00 $53.00

JEDEC JESD 22-A115B

JEDEC JESD 22-A115B

ELECTROSTATIC DISCHARGE (ESD) SENSITIVITY TESTING MACHINE MODEL (MM)..

$27.00 $54.00

JEDEC JS 001

JEDEC JS 001

ELECTROSTATIC DISCHARGE SENSITIVITY TESTING, HUMAN BODY MODEL (HBM) - COMPONENT LEVEL..

$39.00 $78.00

JEDEC JESD 47G.01

JEDEC JESD 47G.01

STRESS-TEST-DRIVEN QUALIFICATION OF INTEGRATED CIRCUITS..

$34.00 $67.00