• JEDEC JESD22-B109B

JEDEC JESD22-B109B

  • FLIP CHIP TENSILE PULL
  • standard by JEDEC Solid State Technology Association, 07/01/2014
  • Category: JEDEC

$56.00 $28.00

The Flip Chip Tensile Pull Test Method is performed to determine the fracture mode and strength of the solder bump interconnection between the flip chip die and the substrate. It should be used to assess the consistency of the chip join process. This test method is a destructive test.
PDF

All of our standards document are available in PDF (Portable Document Format), an electronic, downloadable format.You will be able to download the file in your account downloads.

Multi-User Access

After purchasing, you have the ability to assign each license to a specific user.

Printable

At any time, you are permitted to make printed copies for your and your members' reference use.

JEDEC JESD68.01

JEDEC JESD68.01

COMMON FLASH INTERFACE (CFI)..

$30.00 $60.00

JEDEC JESD65B

JEDEC JESD65B

DEFINITION OF SKEW SPECIFICATIONS FOR STANDARD LOGIC DEVICES..

$30.00 $60.00

JEDEC JESD 31C

JEDEC JESD 31C

GENERAL REQUIREMENTS FOR DISTRIBUTORS OF COMMERCIAL AND MILITARY SEMICONDUCTOR DEVICES..

$34.00 $67.00

JEDEC JEP147

JEDEC JEP147

PROCEDURE FOR MEASURING INPUT CAPACITANCE USING A VECTOR NETWORK ANALYZER (VNA)..

$27.00 $53.00