• JEDEC JESD47K

JEDEC JESD47K

  • STRESS-TEST-DRIVEN QUALIFICATION OF INTEGRATED CIRCUITS
  • standard by JEDEC Solid State Technology Association, 08/01/2018
  • Category: JEDEC

$76.00 $38.00

This standard describes a baseline set of acceptance tests for use in qualifying electronic components as new products, a product family, or as products in a process which is being changed.
PDF

All of our standards document are available in PDF (Portable Document Format), an electronic, downloadable format.You will be able to download the file in your account downloads.

Multi-User Access

After purchasing, you have the ability to assign each license to a specific user.

Printable

At any time, you are permitted to make printed copies for your and your members' reference use.

JEDEC JESD89-2A

JEDEC JESD89-2A

TEST METHOD FOR ALPHA SOURCE ACCELERATED SOFT ERROR RATE..

$30.00 $60.00

JEDEC JESD61A.01

JEDEC JESD61A.01

ISOTHERMAL ELECTROMIGRATION TEST PROCEDURE..

$44.00 $87.00

JEDEC JESD69B

JEDEC JESD69B

INFORMATION REQUIREMENTS FOR THE QUALIFICATION OF SILICON DEVICES..

$27.00 $54.00

JEDEC JEP114.01

JEDEC JEP114.01

GUIDELINES FOR PARTICLE IMPACT NOISE DETECTION (PIND) TESTING, OPERATOR TRAINING, AND CERTIFICATION..

$39.00 $78.00