• JEDEC JESD71

JEDEC JESD71

  • STANDARD TEST AND PROGRAMMING LANGUAGE (STAPL)
  • standard by JEDEC Solid State Technology Association, 08/01/1999
  • Category: JEDEC

$87.00 $44.00

STAPL is a vendor- and platform-independent language for programming and testing devices via the IEEE standard 1149.1 interface, commonly known as JTAG. STAPL enables programming of designs into programmable logic devices (PLDs) offered by a variety of PLD vendors. STAPL is also suitable for testing 1149.1-compliant devices.
PDF

All of our standards document are available in PDF (Portable Document Format), an electronic, downloadable format.You will be able to download the file in your account downloads.

Multi-User Access

After purchasing, you have the ability to assign each license to a specific user.

Printable

At any time, you are permitted to make printed copies for your and your members' reference use.

JEDEC JESD 12-3

JEDEC JESD 12-3

ADDENDUM No. 3 to JESD12 - CMOS GATE ARRAY MACROCELL STANDARD..

$30.00 $59.00

JEDEC JESD531 (R2002)

JEDEC JESD531 (R2002)

THERMAL RESISTANCE TEST METHOD FOR SIGNAL AND REGULATOR DIODES (FORWARD VOLTAGE, SWITCHING METHOD)..

$30.00 $59.00

JEDEC JESD7-A

JEDEC JESD7-A

STANDARD FOR DESCRIPTION OF 54/74HCXXXX AND 54/74HCTXXXX HIGH SPEED CMOS DEVICES..

$71.00 $141.00

JEDEC JEP64 (R2002)

JEDEC JEP64 (R2002)

SOLID STATE PRODUCTS REGISTRATION LIST(ORDER FROM TYPE ADMINISTRATION OFFICE)..

$104.00 $208.00