JEDEC JESD78E
- IC LATCH-UP TEST
- standard by JEDEC Solid State Technology Association, 04/01/2016
- Category: JEDEC
$74.00
$37.00
This standard covers the I-test and Vsupply overvoltage latch-up testing of integrated circuits. The purpose of this standard is to establish a method for determining IC latch-up characteristics and to define latch-up detection criteria. Latch-up characteristics are extremely important in determining product reliability and minimizing No Trouble Found (NTF) and Electrical Overstress (EOS) failures due to latch-up. This test method is applicable to NMOS, CMOS, bipolar, and all variations and combinations of these technologies.
This standard has been adopted by the Defense Logistics Agency (DLA) as project 5962-1880.
This standard has been adopted by the Defense Logistics Agency (DLA) as project 5962-1880.
PDF
All of our standards document are available in PDF (Portable Document Format), an electronic, downloadable format.You will be able to download the file in your account downloads.
Multi-User Access
After purchasing, you have the ability to assign each license to a specific user.
Printable
At any time, you are permitted to make printed copies for your and your members' reference use.
