• JEDEC JESD90

JEDEC JESD90

  • A PROCEDURE FOR MEASURING P-CHANNEL MOSFET NEGATIVE BIAS TEMPERATURE INSTABILITIES
  • standard by JEDEC Solid State Technology Association, 11/01/2004
  • Category: JEDEC

$60.00 $30.00

This document describes an accelerated stress and test methodology for measuring device parameter changes of a single p-channel MOSFET after Negative Bias Temperature Instability (NBTI) stress at dc bias conditions. This document gives a procedure to investigate NBTI stress in a symmetric voltage condition with the channel inverted (VGS < 0) and no channel conduction (VDS = 0).There can be NBTI degradation during channel conduction (VGS < 0, VDS < 0), however, this document does not cover this phenomena.
PDF

All of our standards document are available in PDF (Portable Document Format), an electronic, downloadable format.You will be able to download the file in your account downloads.

Multi-User Access

After purchasing, you have the ability to assign each license to a specific user.

Printable

At any time, you are permitted to make printed copies for your and your members' reference use.

JEDEC JESD 12-3

JEDEC JESD 12-3

ADDENDUM No. 3 to JESD12 - CMOS GATE ARRAY MACROCELL STANDARD..

$30.00 $59.00

JEDEC JESD531 (R2002)

JEDEC JESD531 (R2002)

THERMAL RESISTANCE TEST METHOD FOR SIGNAL AND REGULATOR DIODES (FORWARD VOLTAGE, SWITCHING METHOD)..

$30.00 $59.00

JEDEC JESD7-A

JEDEC JESD7-A

STANDARD FOR DESCRIPTION OF 54/74HCXXXX AND 54/74HCTXXXX HIGH SPEED CMOS DEVICES..

$71.00 $141.00

JEDEC JEP64 (R2002)

JEDEC JEP64 (R2002)

SOLID STATE PRODUCTS REGISTRATION LIST(ORDER FROM TYPE ADMINISTRATION OFFICE)..

$104.00 $208.00